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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com cs4360 24-bit, 192 khz 6-channel d/a converter features 24-bit conversion 102 db dynamic range -91 db thd+n low clock jitter sensitivity digital volume control with soft ramp ? 119 db attenuation ? 1-db step size ? zero crossing click-free transitions atapi mixing logic levels between 5.0 v and 1.8 v +3.3 v or +5 v analog power supply 116 mw with 3.3 v supply popguard technology ? for control of clicks and pops description the cs4360 is a complete 6-channel digital-to-analog system including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture, and a high tolerance to clock jitter. the cs4360 accepts data at audio sample rates from 4 khz to 200 khz, consumes very little power, and oper- ates over a wide power supply range. these features are ideal for cost-sensitive, multi-channel audio systems in- cluding dvd players, a/v receivers, set-top boxes, digital tvs and vcrs, mini-component systems, and mixing consoles. ordering information cs4360-kz -10 to 70 c 28-pin tssop cs4360-kzz -10 to 70 c lead free 28-pin tssop CS4360-DZZ -40 to 85 c lead free 28-pin tssop cdb4360 evaluation board i control port external mute control rst volume control interpolation filter analog filter aout a1 ? dac mixer volume control ? dac analog filter ao utb1 interpolation filter volume control interpolation filter analog filter aout a2 ? dac mixer volume control ? dac analog filter ao utb2 interpolation filter volume control interpolation filter analog filter aout a3 ? dac mixer volume control ? dac analog filter ao ut b3 interpolation filter mclk serial port lrck sclk sd i n1 sd i n2 sd i n3 dif1/scl/cclk dif0/sda/cdin m1/ad0/cs vlc 2 vq filt+ va gnd vd vls mutec1 mutec2 mutec3 m2 gnd jul ?04 ds517f2
cs4360 2 ds517f2 table of contents 1. pin description ........................................................................................................... ........ 5 2. typical connection diagram ...................................................................................... 7 3. characteristics and specifications ................ ........................................................ 8 specified operating conditions ................................................................................. 8 absolute maximum ratings ........................................................................................... 8 analog characteristics (cs4360-kz/kzz) .................................................................. 9 analog characteristics (CS4360-DZZ) ..................................................................... 11 combined interpolation & on-chip analog filter response......................... 13 switching specifications - serial audio interface........................................... 16 switching specifications - control port interface ....................................... 17 switching specifications - control port interface ....................................... 18 dc electrical characteristics................................................................................. 19 digital input characteristics ................................................................................... 19 digital interface specifications.............................................................................. 20 thermal characteristics and specifications .................................................... 20 4. applications .............................................................................................................. ........ 21 4.1 sample rate range/operational mode select ................................................................ 21 4.1.1 stand-alone mode ............................................................................................... 21 4.1.2 control port mode ............................................................................................... 21 4.2 system clocking ........................................................................................................... ... 21 4.3 digital interface format .................................................................................................. .. 22 4.3.1 stand-alone mode ............................................................................................... 22 4.3.2 control port mode .............................................................................................. 23 4.4 de-emphasis control ....................................................................................................... 23 4.4.1 stand-alone mode ............................................................................................... 24 4.4.2 control port mode ............................................................................................... 24 4.5 recommended power-up sequence ............................................................................... 24 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/ important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is sub- ject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products a re sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those 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cs4360 ds517f2 3 4.5.1 stand-alone mode ............................................................................................... 24 4.5.2 control port mode ............................................................................................... 24 4.6 popguard ? transient control .......................................................................................... 24 4.6.1 power-up ............................................................................................................. 24 4.6.2 power-down ........................................................................................................ 24 4.6.3 discharge time ................................................................................................... 25 4.7 mute control .............................................................................................................. ...... 25 4.8 grounding and power supply arrangements .................................................................. 25 4.8.1 capacitor placement ........................................................................................... 25 4.8.2 power supply sections ....................................................................................... 25 4.9 control port interface .................................................................................................... .. 25 4.9.1 memory address pointer (map) ......................................................................... 26 4.9.1a incr (auto map increment) ................. ............................................... 26 4.9.1b map0-3 (memory address pointer) ..................................................... 26 4.9.2 i2c mode ............................................................................................................. 26 4.9.2a i2c write ............................................................................................... 26 4.9.2b i2c read ............................................................................................... 27 4.9.3 spi mode ............................................................................................................ 27 4.9.3a spi write .............................................................................................. 28 5. register quick reference ......................................................................................... 29 6. register descriptions .................................................................................................. 30 6.1 mode control 1 (address 01h) ......................................................................................... 30 6.1.1 auto-mute (amute) bit 7 ....................................................................................... 30 6.1.2 digital interface format (dif) bit 4-6 ...................................................................... 30 6.1.3 de-emphasis control (dem) bit 2-3........................................................................ 31 6.1.4 functional mode (fm) bit 0-1.................................................................................. 31 6.2 invert signal (address 02h) ............................................................................................. 31 6.2.1 invert signal polarity (inv_xx) bit 0-5..................................................................... 31 6.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h)............................................. 31 6.3.1 atapi channel mixing and muting (atapi) bit 0-3................................................... 32 6.4 volume control (addresses 06h - 0bh) ........................................................................... 33 6.4.1 mute (mute) bit 7 ................................................................................................ 33 6.4.2 volume control (xx_vol) bit 0-6................................................................... 33 6.5 mode control 2 (address 0dh) ......................................................................................... 33 6.5.1 soft ramp and zero cross control (szc) bit 6-7............................................. 33 6.5.2 control port enable (cpen) bit 5 ........................................................................... 34 6.5.3 power down (pdn) bit 4......................................................................................... 34 6.5.4 popguard? transient control (popg) bit 3 ........................................................... 34 6.5.5 freeze controls (freeze) bit 2............................................................................. 35 6.5.6 master clock divide enable (mclkdiv) bit 1 ................................................... 35 6.5.7 single volume control (snglvol) bit 0................................................................ 35 6.6 revision register (read only) (address 0dh) ................................................................ 35 6.6.1 revision indicator (rev) [read only] bit 0-3 ......................................................... 35 7. parameter definitions .................................................................................................. 36 total harmonic distortion + noise (thd+n) .......................................................................... 36 dynamic range .................................................................................................................. .... 36 interchannel isolation ......................................................................................................... .... 36 interchannel gain mismatch................................................................................................... 36 gain error ..................................................................................................................... .......... 36 gain drift ..................................................................................................................... ........... 36
cs4360 4 ds517f2 8. references ................................................................................................................ ........ 36 9. package dimensions ....................................................................................................... 3 7 list of figures figure 1. typical connection diagram .......................................................................................... 7 figure 2. output test load ..................................................................................................... .... 10 figure 3. maximum loading ...................................................................................................... .. 10 figure 4. single-speed stopband rejection ................................................................................ 14 figure 5. single-speed transition band ...................................................................................... 14 figure 6. single-speed transition band (detail) ......................................................................... 14 figure 7. single-speed passband ripple .................................................................................... 14 figure 8. double-speed stopband rejection .............................................................................. 14 figure 9. double-speed transition band ..................................................................................... 14 figure 10. double-speed transition band (detail) ........................................................................ 15 figure 11. double-speed passband ripple ................................................................................... 15 figure 12. serial mode input timing ............................................................................................ .16 figure 13. control port timing - i2c mode .................................................................................... 17 figure 14. control port timing - spi mode ................................................................................... 18 figure 15. left justified up to 24-bit data .................................................................................... .23 figure 16. i 2 s, up to 24-bit data ................................................................................................... 23 figure 17. right justified data ................................................................................................ ...... 23 figure 18. de-emphasis curve ................................................................................................... .. 23 figure 19. i2c write ........................................................................................................... ............ 27 figure 20. i2c read ............................................................................................................ ........... 27 figure 21. spi write ........................................................................................................... ........... 28 figure 22. atapi block diagram ................................................................................................. .32 list of tables table 1. cs4360 stand-alone operational mode............................................................................. 21 table 2. cs4360 control port operational mode............................................................................. 21 table 3. single-speed mode standard frequencies ........................................................................ 21 table 4. double-speed mode standard frequencies ....................................................................... 21 table 5. quad-speed mode standard frequencies ......................................................................... 22 table 6. digital interface format - stand-alone mode...................................................................... 22 table 7. power supply control sections ......................................................................................... .25 table 8. digital interface formats - control port mode .................................................................... 30 table 9. atapi decode.......................................................................................................... .......... 32 table 10. example digital volume settings ..................................................................................... 3 3
cs4360 ds517f2 5 1. pin description vls mutec1 sdin1 aouta1 sdin2 aoutb1 sdin3 mutec2 sclk aouta2 lrck aoutb2 mclk va vd gnd gnd aouta3 rst aoutb3 dif1/scl/cclk mutec3 dif0/sda/cdin vq m1/ad0/cs filt+ vlc m2 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 cs4360
cs4360 6 ds517f2 pin name # pin description vls 1 serial audio interface power ( input ) - positive power for the serial audio interface. sdin1 sdin2 sdin3 2 3 4 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 5 serial clock ( input ) - serial clock for the serial audio interface. lrck 6 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 7 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 8 digital power ( input ) - positive power supply for the digital section. gnd 9 21 ground ( input ) rst 10 reset ( input ) - powers down device and resets all internal resisters to their default settings. vlc 14 control port interface power ( input ) - positive power for the control port interface. filt+ 16 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. vq 17 quiescent voltage ( output ) - filter connection for internal quiescent voltage. va 22 analog power ( input ) - positive power supply for the analog section. aoutb3 aouta3 aoutb2 aouta2 aoutb1 aouta1 19 20 23 24 26 27 analog outputs ( output ) - the full scale analog line output level is specified in the analog characteris- tics and specifications table. mutec3 mutec2 mutec1 18 25 28 mute control ( output ) - control signal for optional mute circuit. control port definitions scl/cclk 11 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 12 serial control data i/o ( input/output ) - input/output for i2c data. input for spi data. ad0/cs 13 address bit / chip select ( input ) - chip address bit in i2c mode. control signal used to select the chip in spi mode. stand-alone definitions dif1 dif0 11 12 digital interface format ( input ) - defines the required relationship between the left right clock, serial clock and serial audio data. m1 m2 13 15 mode selection ( input ) - determines the operational mode of the device.
cs4360 ds517f2 7 2. typical connection diagram 21 digital audio source vls gnd cs4360 mclk va aouta1 5 4 3 8 0.1 f + 1 f +3.3 v to +5 v * c/ mode configuration 13 10 12 sdin1 6 dif1/scl/cclk dif0/sda/cdin m1/ad0/cs rst mutec1 optional mute circuit 3.3 f 0.1 f aouta1 c = 4 fs(r 560) l r l + + 16 17 filt+ vq 11 15 m2 7 lrck sclk sdin3 sdin2 3.3 f 10 k ? c 560 ? + 28 27 3.3 f 10 k ? c 560 ? + 26 aoutb1 r l optional mute circuit aouta2 r l 3.3 f 10 k ? c 560 ? + 25 24 3.3 f 10 k ? c 560 ? + 23 aoutb2 r l optional mute circuit aouta3 r l 3.3 f 10 k ? c 560 ? + 18 20 3.3 f 10 k ? c 560 ? + 19 aoutb3 r l aoutb1 0.1 f 3.3 f aouta2 mutec2 aoutb2 aouta3 mutec3 aoutb3 vd 0.1 f + 1 f gnd 9 0.1 f +1.8 v to +5 v * vlc 0.1 f +1.8 v to +5 v * r l +560 +3.3 v to va * * all supplies can be tied together 22 1 14 2 figure 1. typical connection diagram
cs4360 8 ds517f2 3. characteristics and specifications typical performance characteristics are derived from measurements taken at t a = 25 c. min/max performance characteristics and specifications are guaranteed over the operating temperature and voltages. specified operating conditions gnd = 0 v; all voltages with respect to gnd. absolute maximum ratings gnd = 0 v; all voltages with respect to gnd. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. nominal vd supply must be less than or equal to the nominal va supply. 2. any pin except supplies. parameters symbol min typ max units dc power supply analog 3.3 v nominal (note 1) 5.0 v nominal va 3.0 4.5 3.3 5 3.6 5.5 v v digital 2.5 v nominal (note 1) 3.3 v nominal 5.0 v nominal vd 2.25 3.0 4.5 2.5 3.3 5 2.75 3.6 5.5 v v v serial audio interface 1.8 v nominal 2.5 v nominal 3.3 v nominal 5.0 v nominal vls 1.7 2.25 3.0 4.5 1.8 2.5 3.3 5 1.9 2.75 3.6 5.5 v v v v control port interface 1.8 v nominal 2.5 v nominal 3.3 v nominal 5.0 v nominal vlc 1.7 2.25 3.0 4.5 1.8 2.5 3.3 5 1.9 2.75 3.6 5.5 v v v v parameters symbol min max units dc power supply analog digital serial audio interface control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 2) i in -10ma digital input voltage serial audio interface control port interface v ind_s v ind_c -0.3 -0.3 vls+0.4 vlc+0.4 v v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs4360 ds517f2 9 analog characteristics (cs4360-kz/kzz) test conditions (unless otherwise specified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l =10k ? , c l = 10 pf (see figure 2). all supplies = va = 5.0 v or 3.3 v. notes: 3. one-half lsb of triangular pdf dither is added to data. parameter 5.0 v 3.3 v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range (note 3) unweighted a-weighted a-weighted 94 97 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -86 - - - - - -91 -74 -34 -86 - - db db db double-speed mode fs = 96 khz dynamic range (note 3) unweighted a-weighted 40 khz bandwidth a-weighted 94 97 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -86 - - - - - -91 -74 -34 -86 - - db db db quad-speed mode fs = 192 khz dynamic range (note 3) unweighted a-weighted 40 khz bandwidth a-weighted 94 97 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -86 - - - - - -91 -74 -34 -86 - - db db db
cs4360 10 ds517f2 analog characteristics (cs4360-kz/kzz) (continued) 4. refer to figure 3. . parameters symbol min typ max units dynamic performance for all modes interchannel isolation (1 khz) - 102 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale output voltage 0.60va 0.66va 0.72va vpp output impedance z out - 100 - ? minimum ac-load resistance (note 4) r l -3-k ? maximum load capacitance (note 4) c l - 100 - pf aoutx agnd 3.3 f v out r l c l + figure 2. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 3. maximum loading
cs4360 ds517f2 11 analog characteristics (CS4360-DZZ) test conditions (unless otherwise specified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l = 10 k ? , c l = 10 pf (see figure 2). all supplies = va = 5.0 v and 3.3 v. parameter va = 5.0 v va = 3.3 v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range (note 3) unweighted a-weighted a-weighted 89 92 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -84 - - - - - -91 -74 -34 -84 - - db db db double-speed mode fs = 96 khz dynamic range (note 3) unweighted a-weighted 40 khz bandwidth a-weighted 89 92 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -84 - - - - - -91 -74 -34 -84 - - db db db quad-speed mode fs = 192 khz dynamic range (note 3) unweighted a-weighted 40 khz bandwidth a-weighted 89 92 - 99 102 100 - - - 89 92 - 94 97 97 - - - db db db total harmonic distortion + noise (note 3) 0 db -20 db -60 db - - - -91 -79 -39 -84 - - - - - -91 -74 -34 -84 - - db db db
cs4360 12 ds517f2 analog characteristics (CS4360-DZZ) (continued) parameters symbol min typ max units dynamic performance for all modes interchannel isolation (1 khz) - 102 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale output voltage 0.60va 0.66va 0.72va vpp output impedance z out - 100 - ? ac-load resistance (note 4) r l 3- -k ? load capacitance (note 4) c l --100pf
cs4360 ds517f2 13 combined interpolation & on-chip analog filter response the filter characteristics and the x-axis of the response plots have been normalized to the sample rate (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs. notes: 5. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 6. de-emphasis is only available in single-speed mode. parameter min typ max unit single-speed mode (4 khz to 50 khz sample rates) passband to -0.05 db corner to -3 db corner 0 0 - - 0.4535 0.4998 fs fs frequency response 10 hz to 20 khz -0.02 - +0.035 db stopband 0.5465 - - fs stopband attenuation (note 5) 50 - - db group delay - 9/fs - s de-emphasis error (relative to 1 khz) (note 6) control port mode fs = 32 khz fs = 44.1 khz fs = 48 khz stand-alone mode fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - - - - - - - +0.2/-0.1 +0.05/-0.14 +0/-0.22 +1.5/-0 +0.05/-0.14 +0.2/-0.4 db db db db db db double-speed mode (50 khz to 100 khz sample rates) passband to -0.1 db corner to -3 db corner 0 0 - - 0.4621 0.4982 fs fs frequency response 10 hz to 20 khz -0.1 - 0 db stopband 0.577 - - fs stopband attenuation (note 5) 55 - - db group delay - 4/fs - s quad-speed mode - (100 khz to 200 khz sample rates) passband to -3 db corner 0 - 0.25 fs frequency response 10 hz to 20 khz -0.7 - 0 db group delay - 1.5/fs - s
cs4360 14 ds517f2 figure 4. single-speed stopband rejection figure 5. single-speed transition band figure 6. single-speed transition band (detail) figure 7. single-speed passband ripple figure 8. double-speed stopband rejection figure 9. double-speed transition band
cs4360 ds517f2 15 figure 10. double-speed transition band (detail) figure 11. double-speed passband ripple
cs4360 16 ds517f2 switching specifications - serial audio interface inputs: logic 0 = gnd, logic 1 = vls. parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 40 60 % input sample rate single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 50 100 200 khz khz khz lrck duty cycle 45 55 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk frequency single-speed mode double-speed mode - - 128xfs 64xfs hz hz quad-speed mode (mclkdiv = 0) - hz quad-speed mode (mclkdiv = 1) - hz sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdinx valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdinx hold time t sdh 20 - ns figure 12. serial mode input timing sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdinx sclk lrck mclk 2 ----------------- mclk 4 -----------------
cs4360 ds517f2 17 switching specifications - control port interface inputs: logic 0 = gnd, logic 1 = vlc notes: 7. data must be held for sufficient time to bridge the transition time, t fc , of scl. 8. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 9. for single-speed mode, for double-speed mode, for quad-speed mode. parameter symbol min max unit i2c mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 7) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 8) t ack - (note 9) ns 5 2 56 f s - ----------------- -- - 5 1 28 f s - ------------------ - - 5 6 4f s - --------------- - - t buf t hdst t lo w t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 13. control port timing - i2c mode
cs4360 18 ds517f2 switching specifications - control port interface (continued) notes: 10. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 11. data must be held for sufficient time to bridge the transition time of cclk. 12. for f sclk < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 10) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl -ns cclk high time t sch -ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 11) t dh 15 - ns rise time of cclk and cdin (note 12) t r2 - 100 ns fall time of cclk and cdin (note 12) t f2 - 100 ns 1 mclk ----------------- 1 mclk ----------------- t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 14. control port timing - spi mode
cs4360 ds517f2 19 dc electrical characteristics gnd = 0 v; all voltages with respect to gnd. notes: 13. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input sampled at the highest f s for each speed mode, and open outputs, unless otherwise specified. 14. i lc measured with no external loading on pin 12 (sda). 15. power down mode is defined as rst = lo with all clocks and data lines held static. 16. valid with the recommended capacitor values on filt+ and vq as shown in figure 1. increasing the capacitance will also increase the psrr. digital input characteristics gnd = 0 v; all voltages with respect to gnd. parameters symbol min typ max units normal operation (note 13) power supply current va = 5.0 v vd = 5.0 v va = 3.3 v vd = 3.3 v vls = 5.0 v vlc = 5.0 v vls = 3.3 v vlc = 3.3 v (note 14) i a i d i a i d i ls i lc i ls i lc - - - - - - - - 22 25 21 14 6 2 2 1 - - - - - - - - ma ma ma ma a a a a power dissipation all supplies = 5.0 v all supplies = 3.3 v - - 235 116 265 128 mw mw power-down mode (note 15) power supply current all supplies = 5.0 v all supplies = 3.3 v - - 16 12 - - a a power dissipation all supplies = 5.0 v all supplies = 3.3 v - - 80 40 - - w w all modes of operation power supply rejection ratio (note 16) 1 khz 60 hz psrr - - 60 40 - - db db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 0.5va 250 0.01 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 250 0.01 - - - v k ? ma mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf
cs4360 20 ds517f2 digital interface specifications gnd = 0 v; all voltages with respect to gnd. thermal characteristics and specifications parameters symbol min max units 1.8 v logic high-level input voltage serial audio control port v ih v ih 80% 80% - - vls vlc low-level input voltage serial audio control port v il v il - 13% 13% vls vlc 2.5 v logic high-level input voltage serial audio control port v ih v ih 70% 70% - - vls vlc low-level input voltage serial audio control port v il v il - 13% 13% vls vlc 3.3 v logic high-level input voltage serial audio control port v ih v ih 70% 70% - - vls vlc low-level input voltage serial audio control port v il v il - 13% 13% vls vlc 5.0 v logic high-level input voltage serial audio control port v ih v ih 70% 70% - - vls vlc low-level input voltage serial audio control port v il v il - 13% 13% vls vlc parameters symbol min typ max units package thermal resistance tssop (-kz/kzz & -dzz) ja -40-c/watt ambient operating temperature (power applied) -kz/kzz -dzz t a -10 -40 - - +70 +85 c c
cs4360 ds517f2 21 4. applications 4.1 sample rate range/operational mode select 4.1.1 stand-alone mode the device operates in one of four operational modes determined by the mode pins in stand-alone mode. sample rates outside the specified range for each mode are not supported. 4.1.2 control port mode the device operates in one of three operational modes determined by the fm bits (see section 6.1.4) in control port mode. sample rates outside the specified range for each mode are not supported. 4.2 system clocking the device requires external generation of the master (mclk), left/right (lrck) and serial (sclk) clocks. the lrck, defined also as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratios. the specified ratios of mclk to lrck, along with several standard audio sample rates and the required mclk frequency, are illustrated in tables 3-5. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x* 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. double-speed mode standard frequencies m2 m1 input sample rate (f s )mode 0 0 4 khz - 50 khz single-speed (without de-emphasis) 0 1 32 khz - 48 khz single-speed (with de-emphasis) 1 0 50 khz - 100 khz double-speed 1 1 100 khz - 200 khz quad-speed table 1. cs4360 stand-alone operational mode fm1 fm0 input sample rate (f s )mode 0 0 4 khz - 50 khz single-speed 0 1 50 khz - 100 khz double-speed 1 0 100 khz - 200 khz quad-speed 1 1 reserved reserved table 2. cs4360 control port operational mode
cs4360 22 ds517f2 *requires mclkdiv bit = 1 in the mode control 2 register (address 0ch) 4.3 digital interface format the device will accept audio samples in 1 of 4 digital interface formats in stand-alone mode, as illustrated in table 6, and 1 of 6 formats in control port mode, as illustrated in table 8. 4.3.1 stand-alone mode the desired format is selected via the dif1 and dif0 pins. for an illustration of the required relationship between the lrck, sclk and sdin, see figures 15-17. sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x* 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 5. quad-speed mode standard frequencies dif1 dif0 description format figure 00 left justified, up to 24-bit data 016 01 i 2 s, up to 24-bit data 115 10 right justified, 16-bit data 217 11 right justified, 24-bit data 317 table 6. digital interface format - stand-alone mode
cs4360 ds517f2 23 4.3.2 control port mode the desired format is selected via the dif2, dif1 and dif0 bits in the mode control 2 register (see section 6.1.2). for an illustration of the required relationship between lrck, sclk and sdin, see figures 15-17. 4.4 de-emphasis control the device includes on-chip digital de-emphasis. figure 18 shows the de-emphasis curve for f s equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. notes: de-emphasis is only available in single-speed mode. lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb ls b figure 15. left justified up to 24-bit data lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb figure 16. i 2 s, up to 24-bit data lrck sclk left channel sdin +6 +5 +4 +3 +2+1 +7 -1 -2 -3 -4 -5 lsb right channel msb lsb +6 +5 +4 +3 +2+1 +7 -1 -2 -3 -4 -5 msb lsb figure 17. right justified data gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 18. de-emphasis curve
cs4360 24 ds517f2 4.4.1 stand-alone mode the operational mode pins, m2 and m1, selects the 44.1 khz de-emphasis filter. please see section 4.1 for the desired de-emphasis control. 4.4.2 control port mode the mode control bits selects either the 32, 44.1, or 48 khz de-emphasis filter. please see section 6.1.3 for the desired de-emphasis control. 4.5 recommended power-up sequence 4.5.1 stand-alone mode 1) hold rst low until the power supply and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. in this state, the control port is reset to its default settings and vq will remain low. 2) bring rst high. the device will remain in a low power state with vq low and will initiate the stand- alone power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). 4.5.2 control port mode 1) hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. in this state, the control port is reset to its default settings and vq will remain low. 2) bring rst high. the device will remain in a low power state with vq low. 3) load the desired register settings while keeping the pdn bit set to 1. 4) set the pdn bit to 0. this will initiate the power-up sequence, which lasts approximately 50 s when the popg bit is set to 0. if the popg bit is set to 1, see section 4.6 for a complete description of pow- er-up timing. 4.6 popguard ? transient control the cs4360 uses a novel technique to minimize the effects of output transients during power-up and pow- er-down. this technology, when used with external dc-blocking capacitors in series with the audio out- puts, minimizes the audio transients commonly produced by single-ended single-supply converters. it is activated inside the dac when the rst pin or pdn bit is enabled/disabled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.6.1 power-up when the device is initially powered-up, the audio outputs, aoutax and aoutbx, are clamped to gnd. following a delay of approximately 1000 lrck cycles, each output begins to ramp toward the quiescent voltage. approximately 10,000 lrck cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 4.6.2 power-down to prevent transients at power-down, the device must first enter its power-down state. when this occurs, audio output ceases and the internal output buffers are disconnected from aoutax and aoutbx. in their place, a soft-start current sink is substituted which allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
cs4360 ds517f2 25 4.6.3 discharge time to prevent an audio transient at the next power-on, the dc-blocking capacitors must fully discharge be- fore turning on the power or exiting the power-down state. if full discharge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance and the output load. for example, with a 3.3 f capacitor, the minimum power-down time will be approximately 0.4 seconds. 4.7 mute control the mute control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1), or if the mclk to lrck ratio is incorrect. these pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the cdb4360 data sheet for a suggested mute circuit. 4.8 grounding and power supply arrangements as with any high-resolution converter, the cs4360 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 1 shows the recommended power arrangements, with va, vd, vls and vlc connected to clean supplies. if the ground planes are split be- tween digital ground and analog ground, the gnd pins of the cs4360 should be connected to the analog ground plane. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the cdb4360 evaluation board demonstrates the optimum layout and pow- er supply arrangements. 4.8.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low-value ceramic ca- pacitor being the closest. to further minimize impedance, these capacitors should be located on the same layer as the dac. if desired, all supply pins may be connected to the same supply, but a decoupling ca- pacitor should still be placed on each supply pin and referenced to analog ground. 4.8.2 power supply sections each power supply pin provides power to specific sections of the cs4360. the logic voltage level for each section must adhere to the corresponding power supply voltage setting. for example: if vlc = 1.8 v; vls = 3.3 v; vd = va = 5 v; then the logic level for all mode configuration inputs must equal 1.8 v. 4.9 control port interface the control port is used to load all the internal register settings (see section 6). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i2c or spi. notes: mclk must be applied during all i2c communication. pin #s description power supply reference 2, 3, 4, 5, 6, 7 serial audio interface inputs vls 10, 11, 12, 13, 15 mode configuration inputs vlc table 7. power supply control sections
cs4360 26 ds517f2 4.9.1 memory address pointer (map) the map byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. during a read operation the byte transmitted after the ack will con- tain the data of the register pointed to by the map (see sections 4.9.1a and 4.9.3 for write/read details). 4.9.1a incr (auto map increment) the device has map auto increment capability enabled by the i ncr bit (the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if i ncr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of successive registers. default = ?0? 0 - disabled 1 - enabled 4.9.1b map0-3 (memory address pointer) default = ?0000? 4.9.2 i2c mode in the i2c mode, data is clocked into and out of the bi-directional serial control data line, sda, by the serial control port clock, scl. there is no cs pin. pin ad0 enables the user to alter the chip address (001000[ad0][r/w ]) and should be tied to vlc or gnd as required, before powering up the device. if the device ever detects a high-to-low transition on the ad0/cs pin after power-up, spi mode will be selected. 4.9.2a i2c write to write to the device, follow the procedure below while adhering to the control port switching specifica- tions in section 3. 1) initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the device, then write to the memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (ack) from the device, then write the desired data to the register pointed to by the map. 4) if the incr bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i2c writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus. 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
cs4360 ds517f2 27 4.9.2b i2c read to read from the device, follow the procedure below while adhering to the control port switching specifi- cations. during this operation it is first necessary to write to the device, specifying the appropriate register through the map. 1) after writing to the map (see section 4.9.1), initiate a repeated start condition to the i2c bus fol- lowed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) signal the end of the address byte by not issuing an acknowledge. the device will then transmit the contents of the register pointed to by the map. the map will contain the address of the last register written to the map. 3) if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. con- tinue providing a clock but do not issue an ack on the bytes clocked out of the device. after all the desired registers are read, initiate a stop condition to the bus. 4) if the incr bit is set to 0 and further i2c reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. if no further reads from other registers are desired, initiate a stop condition to the bus. 4.9.3 spi mode in spi mode, data is clocked into the serial control data line, cdin, by the serial control port clock, cclk (see figure 21 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high-to-low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. sda scl 001000 ad0 w start ack map 1-8 ack data 1-8 ack stop figure 19. i2c write sda scl 001000 ad0 w start ack map 1-8 ack 001000 ad0 r repeated start or aborted w r ite ack data 1-8 (pointed to by map) data 1-8 (pointed to by map) ack stop figure 20. i2c read
cs4360 28 ds517f2 4.9.3a spi write to write to the device, follow the procedure below while adhering to the control port switching specifica- tions in section 3. 1) bring cs low. 2) the address byte on the cdin pin must then be 00100000. 3) write to the memory address pointer, map. this byte points to the register to be written. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and repeat the procedure detailed from step 1. if no further writes to other registers are de- sired, bring cs high. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 21. spi write
cs4360 ds517f2 29 5. register quick reference addr function 7 6 5 4 3 2 1 0 1h mode control 1 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 default 10000000 2h invert signal reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 00000000 3h mixing control p1 reserved reserved reserved reserved p1atapi3 p1atapi2 p1atapi1 p1atapi0 default 00001001 4h mixing control p2 reserved reserved reserved reserved p2atapi3 p2atapi2 p2atapi1 p2atapi0 default 00001001 5h mixing control p3 reserved reserved reserved reserved p3atapi3 p3atapi2 p3atapi1 p3atapi0 default 00001001 6h volume control a1 a1_mute a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 00000000 7h volume control b1 b1_mute b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 00000000 8h volume control a2 a2_mute a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 00000000 9h volume control b2 b2_mute b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 00000000 0ah volume control a3 a3_mute a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 00000000 0bh volume control b3 b3_mute b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 00000000 0ch mode control 2 szc1 szc0 cpen pdn popg freeze mclkdiv snglvol default 10 0 11000 0dh revision indicator reserved reserved reserved reserved rev3 rev2 rev1 rev0 default 0000xxxx
cs4360 30 ds517f2 6. register descriptions note: all registers are read/write in i2c mode and write only in spi, unless otherwise stated. 6.1 mode control 1 (address 01h) 6.1.1 auto-mute (amute) bit 7 default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter out put will mute following the rec eption of 8192 consecutive audio samples of static 0 or 1. a single sample of non-st atic data will rel ease the mute. detection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will become active during the mute period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the power and muting control register. 6.1.2 digital interface format (dif) bit 4-6 default = 000 - format 0 (left justified, up to 24-bit data) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 15-17. 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 10000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 015 001 i 2 s, up to 24-bit data 116 010 right justified, 16-bit data 217 011 right justified, 24-bit data 317 100 right justified, 20-bit data 417 101 right justified, 18-bit data 517 110 reserved -- 111 reserved -- table 8. digital interface formats - control port mode
cs4360 ds517f2 31 6.1.3 de-emphasis control (dem) bit 2-3 default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32-, 44.1- or 48-khz sample rates. (see figure 18.) note: de-emphasis is only available in single-speed mode. 6.1.4 functional mode (fm) bit 0-1 default = 00 00 - single-speed mode (4- to 50-khz sample rates) 01 - double-speed mode (50- to 100-khz sample rates) 10 - quad-speed mode (100- to 200-khz sample rates) 11 - reserved function: selects the required range of input sample rates. 6.2 invert signal (address 02h) 6.2.1 invert signal polarity (inv_xx) bit 0-5 default = 0 0 - disabled 1 - enabled function: when enabled, these bits invert the signal polarity for each of their respective channels. 6.3 mixing control pair 1 (channels a1 & b1) (address 03h) mixing control pair 2 (channels a2 & b2) (address 04h) mixing control pair 3 (channels a3 & b3) (address 05h) 76543210 reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 reserved reserved reserved reserved pxatapi3 pxatapi2 pxatapi1 pxatapi0 00001001
cs4360 32 ds517f2 6.3.1 atapi channel mixing and muting (atapi) bit 0-3 default = 1001 - aoutax = l, aoutbx = r (stereo) function: the cs4360 implements the channel mixing functions of the atapi cd-rom specification. refer to table 9 and figure 22 for additional information. note: all mixing functions occur prior to the digital volume control. mixing only occurs in channel pairs. atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2] [(l+r)/2] table 9. atapi decode a channel volume control aout a aout b left channel audio data right channel audio data b channel volume control & mute & mute figure 22. atapi block diagram
cs4360 ds517f2 33 6.4 volume control (addresses 06h - 0bh) 6.4.1 mute (mute) bit 7 default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is affected, similar to attenuation changes, by the soft and zero cross bits. the mutec pin will become active during the mute period if the mute function is enabled for both channels in the pair. 6.4.2 volume control (xx_vol) bit 0-6 default = 0 function: the digital volume control registers allow independent control of the signal levels in 1-db increments from 0 to -119 db. volume settings are decoded as shown in table 10. the volume changes are im- plemented as dictated by the soft ramp and zero cross bits. all volume settings less than -119 db are equivalent to enabling the mute bit. 6.5 mode control 2 (address 0dh) 6.5.1 soft ramp and zero cross control (szc) bit 6-7 default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp and zero cross function: immediate change when immediate change is selected all level c hanges will be implemented im mediately in one step. 76543210 xx_mute xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 0001010 10 -10 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 10. example digital volume settings 76543210 szc1 szc0 cpen pdn popg freeze mclkdiv snglvol 10011000
cs4360 34 ds517f2 zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp and zero cross soft ramp and zero cross dictates that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and will be implemented on successive signal zero crossings. the 1/8 db level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter zero crossings. the zero cross function is independently monitored and implemented for each channel. 6.5.2 control port enable (cpen) bit 5 default = 0 0 - disabled 1 - enabled function: the control port will become active and reset to the default settings when this function is enabled. 6.5.3 power down (pdn) bit 4 default = 1 0 - disabled 1 - enabled function: the entire device will enter a low-power state when this function is enabled, but the contents of the control registers will be retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur. 6.5.4 popguard? transient control (popg) bit 3 default = 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. please see section 4.6 for implementation details.
cs4360 ds517f2 35 6.5.5 freeze controls (freeze) bit 2 default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to the registers without the changes taking effect until the freeze is disabled. to have multiple changes in the control port registers take effect simulta- neously, enable the freeze bit, make all register changes, then disable the freeze bit. 6.5.6 master clock divide enable (mclkdiv) bit 1 default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2 prior to all other internal circuitry. 6.5.7 single volume control (snglvol) bit 0 default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independently controlled by their respective volume control bytes when this function is disabled. when enabled, the volume on all channels is determined by the a1 channel volume control byte, and the other volume control bytes are ignored. 6.6 revision register (read only) (address 0dh) 6.6.1 revision indicator (rev) [read only] bit 0-3 default = none 0001 - revision a 0010 - revision b 0011 - revision c etc. function: this read-only register indicates the revision level of the device. 76543210 reserved reserved reserved reserved rev3 rev2 rev1 rev0 0000 xxxx
cs4360 36 ds517f2 7. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the spec- ified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-t o-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 8. references 1) cdb4360 evaluation board datasheet 2) ?the i2c bus specification: version 2.1? philips semiconduc tors, january 2000. http://www.semiconductors.philips.com
cs4360 ds517f2 37 9. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a-- --0.47-- --1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

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